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HD74AC166/HD74ACT166
8-bit Shift Register
REJ03D0255-0200Z (Previous ADE-205-375 (Z)) Rev.2.00 Jul.16.2004
Description
The HD74AC166/HD74ACT166 is an 8-bit, serial or parallel-in, serial-out shift register using edge triggered D-type flip-flops. Serial and parallel entry are synchronous, with state changes initiated by the rising edge of the clock. An asynchronous Master Reset overrides other inputs and clears all flip-flops. The circuit can be clocked from two sources or one CP input can be used to trigger the other.
Features
* Outputs Source/Sink 24 mA * HD74ACT166 has TTL-Compatible Inputs * Ordering Information: Ex. HD74AC166
Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) FP-16DAV TTP-16DAV FP RP T EL (2,000 pcs/reel) EL (2,500 pcs/reel) ELL(2,000 pcs/reel)
HD74AC166AFPEL SOP-16 pin (JEITA) HD74AC166TELL TSSOP-16 pin
HD74AC166ARPEL SOP-16 pin (JEDEC) FP-16DNV
Notes: 1. Please consult the sales office for the above package availability. 2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of the package code.
Pin Arrangement
DS 1 P0 2 P1 3 P2 4 P3 5 CP2 6 CP1 7 GND 8 (Top view) 16 VCC 15 PE 14 P7 13 Q7 12 P6 11 P5 10 P4 9 MR
Rev.2.00, Jul.16.2004, page 1 of 8
HD74AC166/HD74ACT166
Logic Symbol
15 2 3 4 5 10 11 12 14
PE P0 P1 P2 P3 P4 P5 P6 P7 1 7 6 1 2 DS CP MR Q7
9
13 VCC=Pin16 GND=Pin8
Pin Names
CP1, CP2 DS PE P0 to P7 MR Q7 Clock Pulse Inputs (Active Rising Edge) Serial Data Input Parallel Enable Input (Active Low) Parallel Data Inputs Asynchronous Master Reset Input (Active Low) Last Stage Output
Functional Description
Operation is synchronous (except for Master Reset) and state changes are initiated by the rising edge of either clock input if the other clock input is Low. When one of the clock inputs is used as an active High clock inhibt, it should attain the High state while the other clock is still in the High state following the previous operation. When the Parallel Enable (PE) input is Low, data is loaded into the register from the Parallel Data (P0 to P7) inputs on the next rising edge of the clock. When PE is High, information is shifted from the Serial Data (DS) input to Q0 and all data in the register is shifted one bit position (i.e., Q0 Q1, Q1 Q2, etc.) on the rising edge of the clock.
Truth Table
Inputs MR L H H H H H H: L: X: : X X L H H X PE X L L L L H CP2 X L CP1 X X X H L X DS Parallel P0 to P7 X X a *** h X X X L QA0 a H L QA0 Internal Outputs Q0 Q6 L QB0 b QAn QAn QB0 L QH0 h QGn QGn QH0 Output Q7
High Voltage Level Low Voltage Level Immaterial Low-to-High Clock Transition
Rev.2.00, Jul.16.2004, page 2 of 8
HD74AC166/HD74ACT166
Logic Diagram
P0 DS P1 P2 P3 P4 P5 P6 MR P7 PE CP 12
R CP S CD Q
R CP S CD Q Q7
Absolute Maximum Ratings
Item Supply voltage DC input diode current DC input voltage DC output diode current DC output voltage DC output source or sink current DC VCC or ground current per output pin Storage temperature Symbol VCC IIK VI IOK VO IO ICC, IGND Tstg Ratings -0.5 to 7 -20 20 -0.5 to Vcc+0.5 -50 50 -0.5 to Vcc+0.5 50 50 -65 to +150 Unit V mA mA V mA mA V mA mA C VI = -0.5V VI = Vcc+0.5V VO = -0.5V VO = Vcc+0.5V Condition
Recommended Operating Conditions: HD74AC166
Item Supply voltage Input and output voltage Operating temperature Input rise and fall time (except Schmitt inputs) VIN 30% to 70% VCC Symbol VCC VI, VO Ta tr, tf Ratings 2 to 6 0 to VCC -40 to +85 8 V V C ns/V VCC = 3.0V VCC = 4.5 V VCC = 5.5 V Unit Condition
Rev.2.00, Jul.16.2004, page 3 of 8
HD74AC166/HD74ACT166
DC Characteristics: HD74AC166
Item Symbol VIH Vcc (V) 3.0 4.5 5.5 VIL 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 VOL 5.5 3.0 4.5 5.5 3.0 4.5 Input leakage current Dynamic output current* Quiescent supply current IIN IOLD IOHD ICC 5.5 5.5 5.5 5.5 5.5 min. 2.1 3.15 3.85 -- -- -- 2.9 4.4 5.4 2.58 3.94 4.94 -- -- -- -- -- -- -- -- -- -- Ta = 25C typ. 1.5 2.25 2.75 1.50 2.25 2.75 2.99 4.49 5.49 -- -- -- 0.002 0.001 0.001 -- -- -- -- -- -- -- max. -- -- -- 0.9 1.35 1.65 -- -- -- -- -- -- 0.1 0.1 0.1 0.32 0.32 0.32 0.1 -- -- 8.0 Ta = -40 to +85C min. max. 2.1 -- 3.15 3.85 -- -- -- 2.9 4.4 5.4 2.48 3.80 4.80 -- -- -- -- -- -- -- 86 -75 -- -- -- 0.9 1.35 1.65 -- -- -- -- -- -- 0.1 0.1 0.1 0.37 0.37 0.37 1.0 -- -- 80 A mA mA A V VOUT = 0.1 V or VCC -0.1 V Unit Condition
Input Voltage
V
VOUT = 0.1 V or VCC -0.1 V
Output voltage
VOH
VIN = VIL or VIH IOUT = -50 A VIN = VIL or VIH IOH = -12 mA IOH = -24 mA IOH = -24 mA VIN = VIL or VIH IOUT = 50 A VIN = VIL or VIH IOL = 12 mA IOL = 24 mA IOL = 24 mA VIN = VCC or GND VOLD = 1.1 V VOHD = 3.85 V VIN = VCC or ground
*Maximum test duration 2.0 ms, one output loaded at a time.
Recommended Operating Conditions: HD74ACT166
Item Supply voltage Input and output voltage Operating temperature Input rise and fall time (except Schmitt inputs) VIN 0.8 to 2.0 V Symbol VCC VI, VO Ta tr, tf Ratings 2 to 6 0 to VCC -40 to +85 8 V V C ns/V VCC = 4.5V VCC = 5.5V Unit Condition
Rev.2.00, Jul.16.2004, page 4 of 8
HD74AC166/HD74ACT166
DC Characteristics: HD74ACT166
Item Symbol VIH VIL Output voltage VOH VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 VOL 5.5 4.5 5.5 4.5 Input current ICC/input current Dynamic output current* Quiescent supply current IIN ICCT IOLD IOHD ICC 5.5 5.5 5.5 5.5 5.5 5.5 min. 2.0 2.0 -- -- 4.4 5.4 3.94 4.94 -- -- -- -- -- -- -- -- -- Ta = 25C typ. 1.5 1.5 1.5 1.5 4.49 5.49 -- -- 0.001 0.001 -- -- -- 0.6 -- -- -- max. -- -- 0.8 0.8 -- -- -- -- 0.1 0.1 0.32 0.32 0.1 -- -- -- 8.0 Ta = -40 to +85C min. max. 2.0 -- 2.0 -- -- 4.4 5.4 3.80 4.80 -- -- -- -- -- -- 86 -75 -- -- 0.8 0.8 -- -- -- -- 0.1 0.1 0.37 0.37 1.0 1.5 -- -- 80 A mA mA mA A V Unit Condition
Input voltage
V
VOUT = 0.1 V or Vcc-0.1 V VOUT = 0.1 V or Vcc-0.1 V VIN = VIL or VIH IOUT = -50 A VIN = VIL VIN = VIL or VIH IOUT = 50 A VIN = VIL VIN = VCC or GND VIN = VCC-2.1 V VOLD = 1.1 V VOHD = 3.85 V VIN = VCC or ground IOL = 24 mA IOL = 24 mA IOH = -24 mA IOH = -24 mA
*Maximum test duration 2.0 ms, one output loaded at a time.
AC Characteristics: HD74AC166
Ta = +25C CL = 50 pF Item Maximum clock frequency Propagation delay CP1 or CP2 to Q7 Propagation delay CP1 or CP2 to Q7 Propagation delay MR to Q7 Note: Symbol fmax tPLH tPHL tPHL VCC (V)*1 Min 3.3 75 5.0 3.3 5.0 3.3 5.0 3.3 5.0 100 1.0 1.0 1.0 1.0 1.0 1.0 Typ -- -- 11.0 9.5 10.5 9.0 9.5 6.5 Max -- -- 14.5 11.5 14.0 11.0 12.0 9.0 Ta = -40C to +85C CL = 50 pF Min 65 80 1.0 1.0 1.0 1.0 1.0 1.0 -- -- 15.5 12.5 15.0 12.0 13.0 10.0 Max MHz ns Unit
1. Voltage Range 3.3 is 3.3 V 0.3 V Voltage Range 5.0 is 5.0 V 0.5 V
Rev.2.00, Jul.16.2004, page 5 of 8
HD74AC166/HD74ACT166
AC Operating Requirements: HD74AC166
Ta = +25C CL = 50 pF Item Setup time PE or Pn or DS to CPn Hold time CPn to PE or Pn or DS Pulse width CPn or MR Recovery time MR to CPn Note: Symbol VCC (V)*1 Typ tsu 3.3 3.0 th tw trec 5.0 3.3 5.0 3.3 5.0 3.3 5.0 2.0 -1.5 -0.5 2.0 2.0 -2.5 -1.5 Ta = -40C to +85C CL = 50 pF Unit ns
Guaranteed Minimum 5.5 6.0 4.0 3.0 3.0 5.5 4.5 0.0 0.0 4.5 3.0 3.0 7.0 5.0 0.0 0.0
1. Voltage Range 3.3 is 3.3 V 0.3 V Voltage Range 5.0 is 5.0 V 0.5 V
AC Characteristics: HD74ACT166
Ta = +25C CL = 50 pF Item Symbol VCC (V)*1 Maximum clock fmax 5.0 frequency Propagation delay tPLH 5.0 CPn to Q7 Propagation delay tPHL 5.0 CPn to Q7 Propagation delay tPHL 5.0 MR to Q7 Note: 1. Voltage Range 5.0 is 5.0 V 0.5 V Min 100 1.0 1.0 1.0 Typ -- 10.0 9.5 8.5 Max -- 12.5 12.0 11.0 Ta = -40C to +85C CL = 50 pF Min 80 1.0 1.0 1.0 -- 13.5 13.0 12.0 Max MHz ns Unit
AC Operating Requirements: HD74ACT166
Ta = -40C to +85C Ta = +25C CL = 50 pF CL = 50 pF Typ Guaranteed Minimum 2.5 0.0 4.5 -2.5 7.0 1.5 7.0 0.5 8.0 1.5 8.0 0.5 ns
Item Setup time PE or Pn or DS to CPn Hold time CPn to PE or Pn or DS Pulse width CPn or MR Recovery time MR to CPn Note:
Symbol VCC (V)*1 tsu th tw trec 5.0 5.0 5.0 5.0
Unit
1. Voltage Range 5.0 is 5.0 V 0.5 V
Capacitance
Item Input capacitance Power dissipation capacitance Symbol CIN CPD 4.5 35.0 Typ pF pF Unit VCC = 5.5 V VCC = 5.0 V Condition
Rev.2.00, Jul.16.2004, page 6 of 8
HD74AC166/HD74ACT166
Package Dimensions
As of January, 2003
10.06 10.5 Max 16 9
5.5
Unit: mm
1
*0.20 0.05
8
0.80 Max
2.20 Max
0.20 7.80 + 0.30 -
1.15
1.27
0.10 0.10
0 - 8
0.70 0.20
*0.40 0.06
0.15
0.12 M
Package Code JEDEC JEITA Mass (reference value) FP-16DAV -- Conforms 0.24 g
*Ni/Pd/Au plating
As of January, 2003
Unit: mm
9.9 10.3 Max 16 9
3.95
1 1.27 0.635 Max
8
0.11 0.14 + 0.04 - 1.75 Max
*0.20 0.05
0.10 6.10 + 0.30 -
1.08
0 - 8
+ 0.67 0.60 - 0.20
*0.40 0.06
0.15 0.25 M
*Ni/Pd/Au plating
Package Code JEDEC JEITA Mass (reference value)
FP-16DNV Conforms Conforms 0.15 g
Rev.2.00, Jul.16.2004, page 7 of 8
HD74AC166/HD74ACT166
As of January, 2003
Unit: mm
5.00 5.30 Max 16 9
4.40
1
*0.20 0.05
8 0.65 0.13 M 0.65 Max
*0.15 0.05
1.0 6.40 0.20 0 - 8 0.50 0.10
1.10 Max
0.10
0.07 +0.03 -0.04
*Ni/Pd/Au plating
Package Code JEDEC JEITA Mass (reference value)
TTP-16DAV -- -- 0.05 g
Rev.2.00, Jul.16.2004, page 8 of 8
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